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Complementary Measurement Techniques for Trace Metal Contamination on Silicon Wafer Surfaces

Views: 0     Author: Site Editor     Publish Time: 2023-08-02      Origin: Site

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Complementary Measurement Techniques for Trace Metal Contamination on Silicon Wafer Surfaces

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The semiconductor industry has high requirements for product quality and cleanliness of the production environment. Metal contamination is harmful to chips, so metal contamination on silicon wafers should be avoided. The purpose of this study is to exchange experience in solving the problem of metal contamination on the surface of silicon wafers, and to introduce how to use complementary measurement techniques to detect trace metal contamination on the wafer surface and find out the root cause of the problem, Explain the difficulty of selecting a suitable method from among multiple detection methods, and explore the dependence of lifetime measurement techniques on heat treatment.

This article aims to address contamination on the surface of silicon substrates and three different examples of metal contamination will be discussed. The first is Ni diffusion, such a fast-diffusing species, which is a metal contamination that diffuses from a spot on the edge of the wafer. The second is Cr pollution, which diffuses from the bulk body region to the initial oxide film and forms a thicker oxide layer on the wafer surface. Finally there is stainless steel contamination on the edge of the wafer. The purpose of this research is to find the source of the pollution according to the pollution characteristics shown inFigure 1.

Figure 1. Micromask defect map of nickel diffusion (left); thicker chromium oxide deposit (middle); electronic wafer inspection (EWS) map of stainless steel contamination on the wafer edge (right)

For the above example, we need to use multiple different measurement tools in conjunction with each other to find the presence of metal contamination.

First, a total reflection X-ray fluorescence analyzer (TXRF) uses X-rays at extremely small angles to excite the surface of a polished silicon wafer to obtain a map of the concentration of metal contaminants on the surface.

Secondly, gas phase decomposition-inductively coupled plasma mass spectrometry (VPD-ICP-MS) ionizes the sample by ionization, and uses a mass spectrometer to separate the ions for quantitative analysis to detect metals and nonmetals at extremely low levels.

The Surface Photovoltage (SPV) method is a non-contact technique used in semiconductor characterization testing based on the analysis of charge induced by illumination in the surface voltage. Both surface charge and illumination can measure surface voltage, oxide thickness, interfacial trap density, mobile charge, minority carrier diffusion length, and generation lifetime.

Microwave Detected Photoconductivity Decay (µ-PCD) carrier lifetime measurement is also a non-contact method used for wafer incoming inspection, quality control, and process monitoring during chip manufacturing. In this method, laser pulses are used to irradiate the silicon oxide layer to generate electron-hole pairs to characterize the carrier recombination lifetime. The concentration transients of evanescent carriers can be monitored using microwave signals.

Dynamic Secondary Ion Mass Spectrometry (DSIMS) can analyze the elemental composition of materials from the surface to a depth of 100 microns or deeper. This method uses a continuously focused primary ion beam to sputter the sample surface, extracts a part of the sample from the ionized material that has been sputtered off, loads it into a double-focusing mass spectrometer, and uses electrostatic and magnetic fields to separate ions according to their mass-to-charge ratio.

The KLA 2367 inspection tool is used to scan the features after the defect, display the degree of defect and the map, and the detection size is limited to more than 0.16μm. The defect detection tool currently uses a die-to-die comparison method.

Ellipsometry is used to measure thickness. It is a non-destructive testing method and is mainly used to determine the optical index of bulk material and the uniformity of thickness of thin layer (≤5nm) deposited or grown on the substrate.

Finally, photoluminescence (PL) spectroscopy is used to characterize the optical and electronic properties of semiconductors. Photoluminescence spectroscopy is a well-established technique for studying the intrinsic and extrinsic electronic structures of semiconductors and semi-insulating materials, helping to determine impurity content, identify defect compounds, and measure the band gap of semiconductors.

EXAMPLE 1: NICKEL – A FAST DIFFUSER

The case was discovered by defect detection equipment. Many wafers showed the same defect signature in the left quarter after etching the active area of the wafer. These wafers are all from the same lot from the same supplier. Several samples are then taken from this batch of incoming bare wafers and analyzed by different measurement techniques. No defects were found by TXRF, VPD-ICP-MS and SPV analysis methods, and all original films were clean and flawless.

This defect was only detected after etching the effective area of the wafer, so it was decided to perform rapid thermal oxidation (RTO) on the sample first, heat it to about 1,300K for about one minute, and then use the SPV method to detect it. A small area of contamination was seen to the side (Fig. 2).

Figure 2. SPV map after thermal oxidation treatment

Figure 2. SPV map after thermal oxidation treatment

Then, the wafer is placed in a furnace and heated to a higher temperature (1,100 K for 5 hours). The exact same features found on the defect inspection equipment were observed on the SPV and µPCD instruments (Fig. 3).

Figure 3. Ni property maps (from left to right) compared with SPV, μPCD and defect detection techniques

Figure 3. Ni property maps (from left to right) compared with SPV, μPCD and defect detection techniques

The VPD-ICP-MS method was used to explore the pollution components and content. As shown in Figure 4, after heat treatment, six points on the wafer surface were measured: three on the right side of the wafer (1, 2, and 3) and three on the left side (4, 5, and 6). The three measurement points on the right have no pollution, and the nickel content in the center point on the left (point 5) is about 18×1010 atoms/cm2. The other two locations on the left (4 and 6) cannot be measured because the VPD scan droplet has actually been lost, a distinctive feature of the high surface roughness of the wafer, consistent with nickel contamination causing stack-up defects.

Figure 4. VPD-ICP-MS analysis point map

Figure 4. VPD-ICP-MS analysis point map

Finally, VPD-ICP-MS analysis performed on the bevel showed that the contamination came from the bevel of the wafer, not the edge. This final information enables suppliers to quickly locate where the wafer is in contact with the metallic substance consisting of nickel.

As can be seen from this example, nickel diffuses rapidly at high temperatures. The results of the same analysis method before and after thermal oxidation are completely different. Furthermore, it highlights the fact that one analysis method is not enough to identify the root cause of a problem, so several different analysis methods need to be used together.

Example 2: Thicker Chromium Oxide Deposition

The main issue in this case was that the in-line initial oxide thickness was out of control, up to four times the control limit, and the thicker oxide was not homogenous, but was located on top of the wafer opposite the kerf. When the wafer was analyzed by full-scan TXRF, chromium contamination was detected on the same wafer area, but not higher oxide thickness (Figure 5). This chromium diffusion during the oxidation of silicon, resulting in an excessively thick oxide layer due to impurities, has been discussed in previous literature.

Figure 5. Initial oxide thickness (left) and Cr full scan TXRF map

Figure 5. Initial oxide thickness (left) and Cr full scan TXRF map

VPD-ICP-MS and TXRF analysis results showed that chromium contamination was only detectable after initial oxidation and was not detected on incoming wafers. The DSIMS pattern results of the bare wafer highlight the differences between the reference wafer and the wafer cut from the bad ingot. On the back of the wafer, it can be observed that there is chromium contamination on the entire LTO (Low Temperature Oxide) layer (0~300nm) and polysilicon layer (800nm), as shown in Figure 6, but there is no chromium contamination in the Bulk body region and the front side.

Figure 6. DSIMS Analysis Results of Incoming Contaminated Wafer Backside

After initial oxidation, the presence of chromium was observed down to a depth of 100 nm from the front surface and on the back surface and to a depth of 1500 nm (Fig. 7).

Figure 7. DSIMS Analysis Results of Contaminated Wafer Backside After Initial Oxidation

Further VPD-ICPMS and TXRF analyzes were performed on the wafer surface with an oxide thickness of 0.8-1 nm, and compared with the reference value of 0.15 nm thickness. Under full-scan TXRF, the average chromium content on the surface of the contaminated wafer is between 13 and 15×1010 atoms/cm2, and the characteristic map is clear. Five different points were taken for VPD-ICP-MS analysis, as shown in Figure 8. The chromium content of spot 1 is the highest at 88×1010 atoms/cm2, the content of spot 2 is 20×1010 atoms/cm2, the content of spot 3 is 5.5×1010 atoms/cm2, and the content of spots 4 and 5 is below the detection limit, about 0.7×1010 atoms/cm2.

Figure 8. VPD-ICP-MS analysis point map

Figure 8. VPD-ICP-MS analysis point map

A number of different tests were then performed to confirm possible cross-contamination either within the initial oxidation furnace or on the initial oxide deoxidation wet scrubbing station. During both tests, the contaminated wafer was sequentially placed between two uncontaminated wafers, as shown in Figure 9. Test results showed that cross-contamination was visible in the furnace. VPD-ICP-MS analyzes the uncontaminated wafer, the chromium content is about 4×1010 atoms/cm2, and the chromium content of the contaminated wafer is about 25×1010 atoms/cm2. No cross-contamination was observed on the wet bench.

Figure 9. Evaluation of cross-contamination in the initial oxidation furnace

Figure 9. Evaluation of cross-contamination in the initial oxidation furnace

To verify that the contaminants could be removed, some initially oxidized wafers were deoxidized and then re-oxidized. The test result is good, the chromium content is 1.15×1010 atoms/cm2, and the reference value is 0.25×1010 atoms/cm2. Finally, some wafers were re-oxidized and no contamination was detected after HV oxidation and tunnel oxidation. Therefore, chromium contamination is not fatal to the chip.

All these experiments are designed so that we can find the source of the contamination. During the deposition process, a large amount of Cr was incorporated into the LTO layer. In fact, these tests ruled out many assumptions, including the fact that the contaminants were exhausted from the process chamber or muffle due to component aging, which could diffuse chromium to the wafer surface.

Example 3: The edge of the wafer is contaminated by stainless steel

The case was discovered during electronic wafer inspection (EWS). All wafers come from the same boule from the same supplier.

Detecting the bevel of the bare wafer, the VPD-ICP-MS test only detects Cu and Al, but does not detect any metal species on the active side of the wafer. After the first heat treatment (rapid thermal treatment RTP) process, on the effective surface of the bare chip, except for a large amount of aluminum, titanium, chromium and copper, there is still no other substance detected. The reference sheet only shows the same amount of aluminum metal.

The defect signatures of the suspect wafers were very clear when SPV measurements were taken after RTP heat treatment, and became even clearer after furnace treatment (Figure 10). During the DSIMS analysis, no effect on thickness measurements or µPCD measurements after RTP was observed, nor was metal contamination in the Epi/Si interface observed.

Figure 10. SPV maps of contaminated wafers after RTP processing (top left), contaminated wafers after RTP+furnace processing (bottom left), reference samples after RTP processing (top right), and reference sample wafers after RTP+furnace processing (bottom right)

Figure 10. SPV maps of contaminated wafers after RTP processing (top left), contaminated wafers after RTP+furnace processing (bottom left), reference samples after RTP processing (top right), and reference sample wafers after RTP+furnace processing (bottom right)

In contrast, after RTP and furnace processing, bare wafers were analyzed by photoluminescence with good results. Some defects are visible on the left and right edges of the wafer, with cutouts on the bottom. Ring features were seen on the contaminated boule after heat treatment. When the photoluminescence map is overlaid with the defect rate map, it can be seen that the diameter of the ring feature is not exactly the same as that of the defect rate map, which can be due to various reasons, such as surface charge or passivation (Figure 11) .

Figure 11. Contaminated bare wafer photoluminescence plot (left) and its overlay with defect rate (right); contaminated bare wafer photoluminescence plot after heat treatment (left) and its overlay with defect rate ( right)

Figure 11. Contaminated bare wafer photoluminescence plot (left) and its overlay with defect rate (right); contaminated bare wafer photoluminescence plot after heat treatment (left) and its overlay with defect rate ( right)

Ultimately, the wafer supplier managed to find the source of the defect and reproduce the problem, which turned out to be a misplaced screw on the production line that scratched the front side of the wafer. Five VPD-ICP-MS analyzes were performed on the affected wafer surface, collecting contaminants on five different radius rings. The first analysis is on a circle with a radius of 0~60mm centered on the wafer, then the radius is 60~70mm, 80~90mm, and finally 90~100mm (the edge of the wafer). No contamination was detected on the 0~90mm circle. However, Ti, Cr, Fe, Co, Cu, and Mo, the contaminants associated with the origin of the defects, were detected on the rings closest to the edge.

Conclusion

Life testing and direct metal contamination analysis are complementary techniques and should be used together. It is important to note that when it comes to detecting and determining metal contamination, there is no perfect measurement technique and each situation is unique.

These examples demonstrate that it is not easy to choose different techniques to detect a problem. The detection of pollutants with life test technology relies on heat treatment. In fact, on bare wafers, the Ni contamination and Cr contamination of Examples 1 and 2 cannot be detected by any SPV, TXRF, or VPD-ICP-MS methods. Only after the wafer was annealed, Ni diffusion occurred and was visible on the SPV, and only after the initial oxidation, thickness measurements showed non-uniform oxide thickness on the wafer surface. Through TXRF and VPD-ICP-MS analysis, it can be characterized as Cr, and due to DSIMS measurement, it was found to exist inside the bulk region of the wafer.

Finally, for Example 3, after heat treatment, ring-shaped contamination at the edge of the wafer became clear in SPV analysis, but only the VPD-ICP-MS method collected specific species at the edge of the wafer, allowing us to identify stainless steel contamination conclusion.


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